Several conventional applications use clock recovery circuits in system on a chip (SOC) environments. Some examples include storage devices (i.e., optical disc and hard disc data retrieval) and serial data channels (i.e., USB, Firewire, serial ATAPI (SATA), etc.). In order to retrieve the data, the embedded data channel clock signal needs to be recovered and reconstructed from the incoming data. In conventional clock recovery systems, data bits are encoded in the data channel by transitions of the pulse edge using a format such as non return to zero (NRZ) or biphase encoding. Some serial data channel systems encode additional information, such as amplitude information, within the data channel. The additional information may be used either to increase data capacity or embedded some side band information. Such an implementation makes clock recovery more challenging since the recovered channel clock needs to have very low jitter in order to sample the data channel amplitude at a precise moment.
Conventional solutions to these problems include (i) using an external discrete clock recovery circuit, (ii) using a special (i.e., expensive) optical loader that presents a recovered clock, and (iii) using a third party PHY (e.g., SATA, USB etc.) chip.
Traditional data recovery circuitry uses a narrow band phase lock loop (PLL). A data channel edge transition does not occur on every clock cycle. Therefore, the PLL bandwidth is reduced so a clock edge without a data transition would not throw the PLL out of an expected operating range (i.e., the PLL behaves more like a “fly wheel” oscillating at the same channel clock frequency). Whenever there is no data transition, a conventional PLL jitters because the phase error increases or decreases the frequency of the voltage control oscillator (VCO) within the PLL. The PLL relies on the fact that eventually a valid data transition edge occurs to correct the frequency error and phase error. In order to “ride over” the bumps caused by error signals generated at the non-data transition edge, loop filters within PLLS are designed to have very low bandwidth. However, using a low bandwidth loop filter causes a PLL to have a very slow response time to any real change of the data channel frequency and phase, thus having jitter performance much lower than a regular PLL.
A traditional digital phase lock loop uses an independent system clock, which needs another oscillator. Also, an independent system clock has limited resolution and does not track with the frequency of the incoming channel clock, thus reducing performance.
It would be desirable to implement a method and/or apparatus for data recovery that has very low clock jitter allowing the data channel amplitude to be sampled at the precise moment.